Metal-oxide-semiconductor ("MOS") electrically programmable read-only memories ("EPROMs") frequently use memory cells that have electrically isolated gates which are referred to as floating gates. Information is stored in the memory cells in the form of charge on the floating gates.
One type of prior EPROM is the flash erasable and electrically programmable read-only memory ("flash EPROM"). The flash EPROM can be programmed by a user, and once programmed, the flash EPROM retains its data until erased. Once programmed, the contents of the flash EPROM can be erased by electrical erasure. The flash EPROM may then be reprogrammed with new codes or data.
One type of prior flash EPROM typically contains content addressable memory ("CAM") cells in addition to a main memory array. Typically, the number of the CAM cells are in the range of a few hundred. The CAM cells typically comprise flash EPROM cells. The CAM cells are used to perform certain configuration and management functions. The CAM cells are programmed before the memory device reaches the end user as a final product. The CAM cells can be programmed to configure the memory device with respect to the device operation (for example, latched inputs, CEBTTL active high, OEBTTL active high, etc.). The CAM cells can also be used to activate (or deactivate) redundancy cells with respect to the main memory array. The redundancy cells are used in place of defective cells of the main memory array.
The CAM cells are typically biased by a bias circuit. FIG. 1 illustrates in circuit diagram form one prior art bias circuit 10 for the prior CAM cells. In FIG. 1, only one prior CAM cell 20 is shown to couple to bias circuit 10 for illustration purpose. CAM cell 20 is formed by two N type flash EPROM transistors 21 and 22. Transistors 21 and 22 each has a floating gate residing underneath the control gate of the transistor. Transistors 25 and 27 are controlled by signals ENABLE1 and ENABLE2 to conduct a high voltage supply of approximately 12 volts to the drain of transistors 21 and 22, respectively, for programming of transistors 21 and 22. Initially, both transistors 21 and 22 are in the erased state (i.e., conducting). To program CAM cell 20 to a logical "zero" state, transistor 21 is typically programmed to become non-conducting. Similarly, to program CAM cell 20 to a logical "one" state, transistor 22 is typically programmed to become non-conducting.
CAM cell 20 also includes transistors 28 and 29 that are coupled to transistors 21 and 22, respectively. Two P-channel transistors 23 and 24 couple the power supply to the drains of transistors 28 and 29, respectively. Transistors 23 and 24 are also referred to as pull-up transistors of CAM cell 20. Once programmed, the conducting one of transistors 21 and 22 of CAM cell 20 is then biased by its respective one of transistors 28 and 29. For example, if CAM cell 20 is programmed to logical "one" state, transistor 21 is conducting and transistor 22 is not conducting. In this case, transistor 28 couples the drain voltage to transistor 21. The functions of transistors 28 and 29 typically include (1) isolating the drains of transistors 23 and 24 from CAM cell transistors 21 and 22, respectively; (2) preventing latch-up or push-back of the CAM cell during programming operation; and (3) providing a constant drain voltage of approximately 1 volt to transistors 21 and 22 during read operations of the CAM cell to avoid any read disturbance problems. If the drain of transistor 21 or 22 is tied to a voltage higher than 1.5 volts for long time, disturbance will occur.
Both transistors 28 and 29 are coupled to bias circuit 10 to receive a BIAS voltage. The BIAS voltage controls transistors 28 and 29 to generate and couple the constant drain voltage to transistors 21 and 22. Bias circuit 10 includes P-channel transistors 11 and 12 and N-channel transistors 13 and 14. P-channel transistor 11 is coupled to the power supply and receives a CE2 control signal to turn on and off the circuit. P-channel transistor 12 acts as a voltage divider and minimizes power noise of the power supply. N-channel transistors 13 and 14 are stacked diodes typically employed to set the voltage level of the BIAS voltage at node 10a at a constant level of approximately 2 volts. Bias circuit 10 supplies the BIAS voltage to CAM cell 20 at node 10a. The constant BIAS voltage applied at the gates of transistors 28 and 29 causes transistors 28 and 29 to supply the constant drain voltage to transistors 21 and 22.
Given that the BIAS voltage applied to transistors 28 and 29 is constant and given that the drain voltage of transistors 21 and 22 (if conducting) depends on the BIAS voltage applied at the gates of transistors 28 and 29 (i.e., the drain voltage is equal to the BIAS voltage minus the threshold voltage of transistors 28 and 29, respectively), the drain voltage of transistors 21 and 22, in this case, is typically maintained at a constant 1 volt voltage level, thus eliminating read disturbance problem and problems due to power supply variations of the power supply.
Disadvantages are, however, associated with such prior art bias circuit. One disadvantage associated is that the circuit consumes a relatively large amount of power. This is due to the fact that transistors 13 and 14 with their intrinsic impedance of stacked diodes, which function as voltage dividers, are typically low impedance transistors. Transistors 13 and 14 typically employ relatively wide width N-channel transistors in the bias circuit to set the voltage level at node 10a to 2 volts. The low impedance of transistors 13 and 14, however, causes more current to flow through these transistors to ground, thus resulting in a relatively large power consumption of the circuit. Replacing transistors 13 and 14 with high impedance transistors simply either causes the voltage level at output node 10a to an undesirable level or slows the recovery of the circuit from power down.
Another disadvantage associated is that the circuit has a relatively longer recovery time to settle the voltage level at node 10a to the steady voltage level of 2 volts from the OFF state when the circuit is coupled to a plurality of CAM cells. The plurality of CAM cells typically represent a relatively large load to the circuit. When the bias circuit is turned on by the low CE2 control signal, a relatively larger amount of current is required for the CAM cells because of the relatively large load. This causes the circuit to slowly raise the voltage level at node 10a to 2 volts, which results in a relatively slow recovery of the circuit from the OFF state.
Another disadvantage associated is that a precharging time for transistor 12 is typically required before the voltage level at node 10a can rise when the circuit is turned on. Whenever transistor 11 is first turned on by the CE2 signal, it couples the power supply to transistor 12. Transistor 12 is then charged by the power supply until it is conducting. The precharging time also contributes to the slow recovery of the circuit from the OFF state. The precharging time is typically in the range of approximately 34 nanoseconds ("ns") because of the large loading resulted from the large number of the CAM cells.